T8111C ICS TRIPLEX Trusted TMR Processor Module

Description:

The Trusted TMR Processor is a fault tolerant design based on a Triple Modular Redundant (TMR) architecture operating in a lock-step configuration. Figure 1 shows, in simplified terms, the basic structure of the Trusted TMR Processor module.

The module contains three Processor fault containment regions (FCR), each containing a NXP PowerQUICC® IITM series Processor and its associated memory (EPROM, DRAM, Flash ROM, and Flash RAM), memory mapped I/O, voter and glue logic circuits. Each Processor FCR has voted two-out-of-three (2oo3) read access to the other two Processor’s FCR memory systems to eliminate divergent operation.

The module’s three Processors store and execute the application program, scan and update the I/O modules and detect system faults. Each Processor executes the application program independently, but in lock-step synchronisation with the other two.

Each Processor has an interface which consists of an input voter, discrepancy detector logic, memory, and an output driver bus interface to the Inter-Module Bus. The output of each Processor is connected by the module connector to a different channel of the triplicated Inter-Module Bus.

Communication between the Trusted TMR Processor and modules in other chassis is via either a Trusted Interface module, such as the Trusted TMR Interface to a Regent+Plus I/O chassis, or an Expander Interface to an Expander chassis. The functions of the four types of module memory are:

• EPROM - Holds module bootstrap loader (this is embedded in an FPGA)
• Flash ROM - Stores module firmware and the application program
• DRAM - Working memory with scaleable capacity
• Flash RAM - Holds data such as event logs and retained program data

The Front Panel contains a fault containment region (FCR D) separate from the other FCRs. It participates in the module voting operations. In addition it performs the following noncritical functions:

• The diagnostics port and maintenance enable keyswitch mounted on the front panel of the Processor.

• The serial communications drivers and the IRIG-B interface. These are accessed through the I/O connector via a T812X adapter unit at the rear of the Processor.

• Sends Fault/Fail signals to external indicators via the adapter units at the rear of the Processor.

Two IRIG-B input standards are available to the Processor; IRIG-B002 and IRIG-B122. The standard used by the Processor is controlled by software setting a flag in the memory. The IRIG-B signals are used to synchronise systems and time-stamp entries in the Sequence of Events (SOE) log.

Three serial communication options are available from the embedded 4-channel Universal Asynchronous Receiver/Transmitter (UART). These are detailed as follows:

• Channel 0 Front Panel Diagnostic Port (RS232)
• Channel 1 Not configured
• Channel 2 Communications Serial Port 2 (RS422/485)
• Channel 3 Communications Serial Port 3 (RS422/485)

The Trusted operating system (Trusted OS) is used in support of the NXP PowerQUICC® IITM series processor architecture. The real time kernel is a high speed, high functionality kernel made for fault tolerant distributed systems. The distributed communication is made transparent over all processors. 
Frequently Asked Questions:
1.What is the Backplane (IMB) Supply of T8111C?
20 Vdc to 32 Vdc

2.What is Retained Variable Storage of T8111C?
4 KB total
1 byte per Boolean
4 bytes per Analogue
5 bytes per Timer

3.When does the warranty period start?
One year from the time the client receives the goods.

Datasheet Link:

T8111C ICS TRIPLEX Trusted TMR Processor Module PDF Datasheet